| Speaker |
Topic |
| Michael Hill, Intel |
Practical challenges with advanced IVR solutions for microprocessors |
| Vanessa Smet, Georgia Tech |
Machine-learning-based optimization: the future of power package design |
| Rajen Murugan, Texas Instruments |
Multiphysics System Co-Design Modeling: State-of-the-Art, Challenges, and Opportunities |
| Matt Kelly, IPC |
Insights from Microelectronic Packaging for Power Packaging Advancement |
| Gordon Elger, Fraunhofer Application Center |
Roadmap for Copper Sintering – Next Interconnect for Power Electronic Module Packaging |
| Habib Mustain, Heraeus |
Die Top System: Advanced interconnect for Power Electronics Module Packaging |
| G. Q. Lu, Virginia Tech |
A Polymer-Nanoparticle Composite for Nonlinear Resistive Field-Grading in Medium-Voltage Power Modules |
| Satish Kumar, Georgia Tech |
Integrated thermal management in power electronics and motors |
| Matt Wilkowski, EnaChip |
Enabling Sustainable Power Electronics Through Miniaturization and Integration of Power Magnetics |
| Mike Hayes, Tyndall |
eSiP (energy source in package) – 3D packaging considerations for self-powered IoT edge devices |
