THE WORLD of PACKAGING TECHNOLOGIES and THE CRITICAL ISSUES
“3D Power Electronics & Additive Manufacturing”
By Dr. Douglas C Hopkins, Professor
North Carolina State University
With the recent availability of essentially chip-scale packaged GaN, the onus is on power electronics designers to expand their packaging understanding to incorporate high-density devices at the module and board level. New post-silicon power devices, i.e. SiC, GaN and GaAs, are performing at unprecedented voltages and current densities, with switching speeds approaching gigahertz, and operating temperatures pushing above 225˚C. Though electro-physical design (packaging) follows established electrical and manufacturing “design rules,” newer processes, such as 3D stacking and 3D printing, can now expand the “design rules” to provide higher densities in speed, weight, and volume.
This tutorial systematically introduces fundamental understanding and resulting “design rules” for circuit and module that push the envelope in speed and density. Fundamental topics include characteristics of the evolving post-silicon devices, such as MosFETs, Cascode JFETs, variations in FET devices, IGBTs and ultra-high-speed diodes; reviews new power electronics packaging techniques for high performance circuits being developed at PREES; summaries new 3D printed power-packaging opportunities for creating 3D and integrated power electronic converters, and gives a case study in using multiphysics modeling before committing to circuit fabrication.
“Materials & Assembly for 3D Integration”
By Dr. Guo-Quan (GQ) Lu, Professor
Researchers in the field of power electronics continuously strive to improve efficiency and power density of switch-mode converters through circuit design and functional integration. Electronic packaging of power devices and modules is critical for sustaining the technology trend of the field. Recent advances in wide bandgap semiconductor devices offer new challenges and opportunities for power electronic packaging. Innovative materials and assembly technologies are needed to enable high switching frequency and reliable operation at high temperatures. In this tutorial, I will present an overview of CPES’s research efforts on development of power module packaging materials and assembly technologies including (1) 3D power module assembly for lowering parasitic inductance and achieving double-side cooling, (2) nanosilver material technology for high-reliability and high-temperature interconnection, and (3) reliability of sintered silver joints and direct-bond metal-ceramic substrates.
“Thermal & Reliability Issues in 3D Integration”
By Dr. Patrick McCluskey, Professor
University of Maryland
Power electronics are becoming ubiquitous in engineered systems, such as home appliances, cell phone towers, aircraft, wind turbines, automobiles, smart grids, and data centers. Recently, the development of highly efficient power electronic devices and systems based on wide bandgap (WBG) semiconductors have allowed these power systems to manage ever larger power levels at higher frequencies over wider temperature ranges with lower power loss. However, these increased power levels combined with increased power densities can lead to higher heat flux and resultant higher junction temperatures in power electronic systems, especially inside the switching module. Realizing these advantages requires new packaging structures.
This tutorial will focus on the thermal management and reliability of the integrated packaging approaches that are being developed to make high packaging density, lower SWaP-C modules a reality. This includes the latest developments in air cooling, single phase liquid and two-phase cooling technologies, thermoelectrics, thermal isolation, and combined cooling schemes together with their interconnection. In addition, the tutorial will discuss the latest power electronics system reliability modeling, including new models for interconnect and cooler failure mechanisms. The tutorial will also discuss the latest techniques in prognostics, condition monitoring, and accelerated testing.