2026 3D-PEIM Keynote, Oral and Poster Presentations

Presenter

Affiliation

Title and Abstract

Francesco Carobolante

IoTissimo

Keynote: 3D-Integrated Vertical Power Delivery: Achieving >100% Perf/W Gains in Multi-kW Chiplet Stacks

Abstract: As AI processors scale toward multi-kW levels, traditional motherboard regulation reaches physical limits due to both losses and reliability. This paper identifies Package-Integrated Voltage Regulators (PIVR) as a mandatory transition for high-density 3D-integrated systems. We evaluate advanced packaging strategies (Landside versus substrate-Embedded PIVR) and their role in overcoming the “power wall” in multi-chiplet architectures.

Our analytical model demonstrates that voltage droop scales linearly with the current density multiplier k, while the resulting Perf/W penalty scales quadratically, since switching energy varies as V². While MBVR guardbands consume up to 43% of supply voltage at workload hot spots in high-density designs, Embedded PIVR achieves a 4:1 reduction in droop, recovering substantial margin. In 3D two-die stacks that double current through a single package footprint, Embedded PIVR improves Perf/Watt by approximately 55% on average and exceeds 100% at hot spots.

Realizing this roadmap is gated by inductor current density, which must reach 6–10 A/mm² to support hotspots and vertical stacks. We conclude that substrate-embedded regulation is a primary “More than Moore” lever, requiring the independent optimization of signal and power metal stacks in next-generation 3D packages.  

Jason Neely

Sandia National Laboratories

Emerging Hi Developments for Power Electronics

Abstract: Heterogeneous integration (HI) for power electronics enables semiconductor power devices, passive components, control circuitry, and thermal management structures to be combined into compact, high-performance packages. HI can improve power density, switching speed, thermal management, and conversion efficiency while reducing system-level integration complexity. This presentation provides an overview of ongoing efforts at Sandia National Laboratories to realize compact, power-dense power converters through heterogeneous integration. The talk will highlight several complementary projects spanning recent and emerging HI approaches. These include point-of-load converters that step typical bus voltages down to ASIC and processor supply levels, boost converters that generate kilovolt-scale outputs on substrates smaller than a square inch, and embedded 100 μm-scale temperature and strain sensors for in-situ health monitoring. These embedded sensors are being developed to detect thermo-mechanical degradation, including solder interconnect damage, before loss of electrical continuity occurs. The presentation will also discuss emerging designs that combine HI with GaN technologies to process hundreds of watts in postage-stamp-sized footprints. We will report on recently demonstrated converter prototypes as well as in-progress developments, illustrating how advanced HI packaging expands the design space for next-generation power electronics in demanding environments. 

Peter Kanschat

Infineon

Power Electronics re-invented: AI As Key Enabler for Power Device Innovation

Abstract: Advances in computing technology are transforming power demands and architectures in datacenters. Starting at the MV grid, this presentation examines the transition from classical to solid state transformers, highlighting the need for efficient high-voltage semiconductor solutions using >2kV SiC devices. Packaging techniques, once limited to industrial applications, have been adapted to meet new challenges, enabling compact and high-performance designs. Within data centers, power supplies must deliver higher power levels, driving a shift from single-phase AC to three-phase AC or DC supply architectures. These changes result in increased DC-link voltages, such as 800V, and a move from ~600V to 1200V devices, making modules a viable option instead of discrete devices. The deployment of semiconductor-based solid state circuit breakers with SiC MOSFET or JFET technologies provides robust protection and safety, with operational requirements that differ greatly from traditional power switching devices and necessitate specialized packaging. At the processor level, advanced system-in-package solutions accommodate high currents at low voltages, optimize vertical power supply paths, and enhance cooling efficiency and switching speed through dedicated packaging strategies. The presentation will demonstrate how these evolving requirements drive technological innovation across the power supply chain, presenting examples and fundamental principles that enable next-generation datacenter power architecture.

Tim Nils Bierwirth

Leibniz Univ Hannover

Scalable and Miniaturized 3D Peek Package for High-Power Density and High-Efficiency DC-DC Converters for High-Performance Computing

Abstract: The rapid expansion of AI data centers requires highly efficient, power-dense DC-DC converters to bridge the gap between 48V power architectures and sub-1V processor requirements. Traditional silicon-based packaging struggles to integrate bulky passive components like inductors, limiting power density and creating wasted volume on PCBs. To address this, a novel 3D heterogeneous integration method uses polyether ether ketone (PEEK) as a scalable, thermally robust carrier material. The streamlined manufacturing process involves laser-drilling vertical interconnect accesses into PEEK substrates, which are then selectively plated with copper without the need for complex masking. Lasers simultaneously structure conductive surface tracks and ablate cavities for the parts. Active and passive components are then embedded into these vertically aligned cavities across the substrates and joined via reflow soldering. This 3D polymer-based approach successfully doubles spatial integration density compared to conventional planar boards by eliminating dead space and maximizing the volume fill factor, all while maintaining full electrical performance. With the future potential to transition from sequential laser processing to injection molding and to add thermal metallization, this simplified process offers a highly scalable, cost-effective pathway for mass-producing compact converters for next-generation computing. 

Presenter

Affiliation

Title and Abstract

Muneaki Kurimoto

Nagoya Univ

Keynote: Material-Driven Electric Field Engineering for Reliable High-Voltage Power Modules: Field Grading Materials and Nanocomposite Dielectrics

Abstract: As power electronics systems continue to advance toward higher voltage and power density, insulation reliability has become a critical factor limiting performance and scalability. In wide bandgap (WBG)-based power modules, strong electric field localization at material interfaces, edges, and complex geometries significantly accelerates partial discharge, dielectric degradation, and premature failure. This work presents a unified, material-driven framework for electric field engineering and insulation reliability enhancement in advanced power modules. The first part focuses on field grading materials as an effective approach to mitigating electric field crowding. In particular, permittivity-graded materials are introduced as a practical implementation, enabling spatial control of electric field distribution through engineered dielectric inhomogeneity. By reducing field concentration at critical regions such as interfaces and terminations, these materials support high-voltage operation in compact and highly integrated module architectures. The second part introduces high electric-field-resistant nanocomposite dielectrics enabled by nano-scale interface engineering. These nanocomposite dielectrics exhibit enhanced breakdown strength and improved long-term reliability under high electric stress, enabled by nano-scale interface engineering and charge transport control. Finally, emerging directions toward co-design across materials, packaging, and system levels are highlighted. Key considerations related to manufacturability, thermal-mechanical interactions, and reliability assessment are addressed, providing insights into future material and process development for advanced power electronics packaging.Micro

Alex Hanson

UT-Austin

Integrated Magnetic Cores: Needs and Unknowns

Abstract: The road toward greater power electronics integration — heterogenous and ultimately monolithic — is impeded most by the integration of magnetic components. It is particularly unlikely that conventional magnetic cores can simply be scaled down to integrated sizes and hyper-planar form factors. Ferrites in particular are poor candidates for the greatest levels of integration due to their high sintering temperatures, yet ferrite-like magnetic performance (esp. core loss) is needed at integration-ready operating frequencies. This conundrum is being resolved at the interface between power electronics design, materials science, and process technology. In this talk, we will explore what performance we actually need out of an integrated magnetic core, how that informs both material and converter design, and the unknowns whose answers will unlock rapid development of integrated magnetics. 

Chuantong Chen

Univ of Osaka

Microsized Silver–Aluminum Sintering Paste with Enhanced Joint Reliability for SiC Power Modules

Abstract: Sliver (Ag) and Copper (Cu) sinter paste joining is a proven bonding technology for SiC power modules application with a good thermal conductivity and which can be performed in low-temperature low-pressure. Ag paste materials are relatively expensive and sintered joints are prone to problems such as migration short circuits . Sintered Cu paste is one of the ideal connection materials in new power device packaging interconnections. Compared with Ag, sintered Cu paste has better thermal cycle capabilities, high electromigration resistance and low raw material costs . However, the sintering of Cu paste joints usually needs to be carried out in a reducing atmosphere to eliminate the harmful effects of surface oxides, but this limits its industrial application. In addition, the high-temperature reliability of Ag and Cu sintering pastes is also a problem, where sintered Ag always faces the problem of structural coarsening during high temperature and sintered Cu faces the problem of oxidation. This paper proposes a novel Ag- aluminum (Al) particles composite paste (Ag-Al paste) to address the high material cost of Ag and the problem of structural coarsening and power cycling reliability. The micro-sized Ag flakes and Al particles with varying mass fractions (0, 15 vol%, 30 vol%, 40 vol%) were mixed . The joint SiC/DBC structures were sintered on a hotplate in the air with the sintering temperature of 250℃ for 30 min. The joint samples underwent a high temperature aging test at 250 ℃ for 100, 500, and 1000 h, respectively. The interface formation and microstructure evolution of sintered Ag and sintered Ag-Al joint were investigated during high temperature aging and thermal shcok reliability process. Electrical insulation reliability is a critical challenge in modern medium- and high-voltage power electronics, particularly with the increasing adoption of wide-bandgap (WBG) devices that operate at higher voltages, faster switching speeds, and elevated temperatures. These operating conditions introduce steep voltage transients (high dv/dt) that intensify electric field concentrations at material interfaces, triple points, and structural discontinuities, significantly increasing the likelihood of partial discharge (PD) inception. PD is a major degradation mechanism that leads to dielectric aging, electrical treeing, and eventual insulation failure, thereby limiting the lifetime and reliability of advanced power modules. Conventional approaches for PD mitigation include geometric field grading, material engineering, and nonlinear dielectric coatings; however, these methods often add complexity or provide limited effectiveness under high-frequency switching conditions. Electret-based insulation has emerged as a promising alternative due to its unique capability to store quasi-permanent electric charge and locally counteract high electric fields. By generating an opposing electric field, electrets can effectively neutralize field intensification at critical regions, thereby suppressing PD initiation independent of waveform or frequency. Despite this potential, practical implementation of electrets in power modules is constrained by material limitations. Organic electrets such as Parylene HT, although effective and thermally stable compared to traditional polymers, may still face integration challenges in high-temperature fabrication processes. To address these limitations, this work explores an inorganic SiO2/Si3N4 electret structure integrated into aluminum nitride (AlN)-based heterogeneously integrated power module (HIPM) substrates, aiming to provide a thermally robust and scalable solution for PD mitigation in next generation power modules.

Peiyuan Sun

Virginia Tech

Effect of a Polymer Nanocomposite on Surface Flashover in Power Converters at High Elevation

Abstract: Surface flashover is a critical concern for power converters operating at high altitudes, where reduced air pressure lowers the breakdown strength of air and increases susceptibility to partial discharge (PD). This work evaluates a nonlinear resistive polymer nanocomposite (PNC) coating as a conformal insulation solution for mitigating electric-field intensification at high-voltage triple points (TPs) in air-exposed regions of power electronic converters. The coating’s structural uniformity, nanoscale particle distribution, and field-dependent electrical behavior are characterized using scanning electron microscopy, atomic force microscopy/electrostatic force microscope, and finite-element simulation. Experimental PD inception voltage (PDIV) and surface flashover breakdown voltage (BV) measurements were performed under atmospheric conditions and at reduced pressures equivalent to altitudes up to 10,000 m. Results show that the PNC coating increases BV by approximately 30% relative to uncoated structures and suppresses observable PD activity prior to breakdown, in contrast to both uncoated and commercially coated samples. 

Presenter

Affiliation

Title and Abstract

Christopher Roper

HRL

Keynote: Phased Array with Innovative Heterogeneously Integrated Thermal Solution

Abstract: Thermal management remains a primary design challenge for 3D Heterogeneously Integrated (3DHI) microsystems, where densely stacked high power devices, intense hot spots, multiple thermal interfaces, and the limited availability of cooling area create significant constraints on performance and reliability. Under the DARPA Minitherms3D program, we are developing an integrated thermal management solution for a >6.8 kW, five active tier 3DHI stack intended to support next generation RF and mixed signal microsystems. In Phase 1, we designed, fabricated, and assembled a three active tier demonstrator with two embedded single phase microchannel cooling tiers to emulate the thermal behavior of a phased array RF front end. The demonstrator incorporates hot spot and background heaters on each active tier to reproduce representative phased array heat loads, targeting combined average power densities of 450 W/cm² across a 30 mm × 30 mm heated footprint. This footprint is segmented into a 20 × 20 array of independently powered unit cells to enable highly granular thermal studies. The stack architecture places a 16-chiplet compound semiconductor tier on top of two Si CMOS tiers, interconnected through TSVs, redistribution layers, and solder capped copper pillars to provide power distribution, thermal sensing, and structural alignment. Efficient heat removal is provided by dual sided single phase microchannel cooling. Coolant is routed through an off chip header designed to distribute flow to both cooling tiers and collect return flow with integrated bypass channels enabling flow access to the upper cooler. Laser cut epoxy preforms and titanium shims create robust, leak tight fluidic interfaces between tiers and between the stack and the header. This presentation details the fabrication of the thermal, electrical, and mechanical components; the 3D assembly process for the 3 active tier + 2 cooling tier stack; and experimental results characterizing thermal performance. The results demonstrate the feasibility of tightly integrated microfluidic cooling for high power 3DHI systems and establish a foundation for the higher power five tier configuration targeted in a subsequent phase. 

Dave Saums

DS&A LLC

Current Challenges and Developments in Single- and Two-Phase Liquid Cooling

Abstract: Increases in power dissipation per module and in module heat flux are determinants of which technologies are most important; assisting industry by identifying significant differences is intended to assist in identifying where newly developing technologies (system concepts, fluids, materials) may be most useful. Identifying how thermal technologies may be applied most effectively in different industry segments with different operating requirements and varying application conditions, is highly useful for both industry component and material manufacturers and system design engineers. 

Ryan Mayberry

Indium Corporation

Implementing a Solder Thermal Interface Material (sTIM) for Cost-Performance Balance in Molded Power Module to Heat Sink Attach

Abstract: Rapid implementation of silicon carbide (SiC) and gallium nitride (GaN) semiconductor die in high-volume power modules in automotive/EV, industrial drives, and energy conversion systems increases demand for high performance, reliable, and cost-effective device packaging solutions. These wide band gap (WBG) devices, typically have a smaller die area versus the silicon semiconductor that is replaced, with equal or greater power dissipation; the net effect is higher heat flux, driving greater need for efficient heat transfer. A critical assembly design choice and process step is the selection of the attachment material and process for the WBG power module and baseplate, air-cooled heat sink, or liquid cold plate. Silver sintering is widely recognized for excellent thermal conductivity, practical coefficient of thermal expansion (CTE), and robust high-temperature operation in these applications. However, the recent sharp upward trend in the silver market price is bringing a new focus on cost and scalability, in addition to manufacturing investment, throughput and overall complexity. On the other end of the spectrum, traditional polymeric phase change materials and silicone-based thermal greases as applied thermal interface materials (TIMs) offer a lower cost solution, but with a heavy reduction in thermal conductivity, known reliability issues for pump-out and dry-out, and therefore overall greater system performance and reliability concerns. This work reviews soldering technology as a practical alternative that delivers a stronger balance between performance and cost of ownership for high-volume manufacturing. Advancements in alloy technology and reliability-enhancing solder preform solutions complement these advantages to make soldering an attractive option for manufacturers seeking scalable and economical solutions without compromising required field reliability and system life. 

Md Rifat E Rasul

ASU

Defect-Aware Thermal Bottleneck Analysis in SiC/Si Heterogeneous Stacks for Advanced Packaging

Abstract: Thermal bottlenecks in heterogeneous semiconductor stacks have become a critical reliability concern for advanced power electronic integration and packaging systems. In this work, we investigate defect-aware thermal transport behavior in SiC/Si heterogeneous structures by combining scanning thermal microscopy (SThM), frequency-domain thermoreflectance (FDTR), and Ginestra-based electrothermal simulations. Particular attention is given to process-induced defects, including threading dislocations and localized surface damage, and their influence on localized heat confinement and cross-plane thermal dissipation. Experimental SThM measurements reveal spatially localized thermal perturbations associated with defect-rich regions, while FDTR measurements are used to validate thermal conductivity values incorporated into the simulation framework. Using Ginestra, we further explore the sensitivity of thermal spreading and heat dissipation pathways to variations in thin-layer thermal conductivity, including pSi and Si(111) layers, as well as defect-induced thermal degradation mechanisms. The study demonstrates how nanoscale defect structures can generate measurable thermal bottlenecks that propagate into package-level thermal inefficiencies in advanced heterogeneous integration platforms. The combined experimental and simulation framework provides insight into defect-driven thermal reliability limitations in next-generation SiC-based packaging systems. 

Presenter

Affiliation

Title and Abstract

Leslie Hwang

ASU

Keynote: Toward AI-Driven Power Electronics Co-Design: Physics-Informed Learning, Topology Generation, and Packaging Optimization

Abstract: Advanced power electronics systems are becoming increasingly constrained by coupled electrical, thermal, and thermomechanical interactions arising from higher power density, heterogeneous integration, and advanced packaging architectures. Traditional multiphysics simulation workflows based on numerical analysis and iterative design optimization remain computationally expensive and difficult to scale across rapidly expanding design spaces. This talk presents recent advances in physics-informed machine learning approaches for accelerated multiphysics analysis in advanced packaging, with emphasis on thermal and thermomechanical modeling. Particular focus is placed on physics-informed neural networks and surrogate modeling frameworks capable of predicting temperature and warpage fields directly from package geometry and floorplan representations while reducing dependence on costly simulation-generated datasets. The talk will discuss critical considerations in developing reliable AI-driven engineering models, including physics fidelity, parameterization strategies, geometric representation, boundary condition encoding, training stability, and generalization across various design configurations. Beyond analysis acceleration, emerging opportunities for applying AI to automated design synthesis will also be explored, including topology generation, component optimization, and electrical-packaging co-design. Finally, the presentation will discuss the long-term evolution toward autonomous engineering agents capable of generating optimized power electronics systems from schematic-level intent through manufacturable physical implementation, enabling closed-loop AI-assisted design workflows for next-generation power electronics. 

John Damoulakis

Cadence

TBD

Mayukh Nandy

ASU

Electro-Thermal Co-Simulation of GaN-on-SiC Power Amplifier Packages: A Die-to-Board Methodology Using Ansys HFSS and Icepak

Abstract: This paper presents an electro-thermal co-simulation methodology for GaN-on-SiC power amplifier packages, integrating Ansys HFSS and Icepak across the full die-to-package-to-board signal and thermal path. The framework enables quantification of RF performance degradation under realistic thermal operating conditions and evaluates the impact of copper heat spreader integration on both junction temperature and RF signal integrity. The proposed methodology addresses a critical gap in advanced RF package design practice and provides a systematic, simulation-driven approach to thermally aware package optimization ahead of fabrication. 

Ben Schuchardt

Purdue Univ

From Chip to Chiller: System-Level Impact of Power Delivery Architecture on Data Center Cooling Costs

Abstract: As GPU and HBM power demands rise, power delivery network (PDN) architecture choices increasingly drive both chip-level thermal behavior and data center cooling cost. Prior work has analyzed PDN thermal effects at the chip level or modeled data center cooling at the facility level but rarely connects the two. This work bridges that gap by quantifying how the choice between a discrete voltage regulator (VR) architecture and an on-interposer integrated voltage regulator (IVR) architecture propagates from the die through the rack to annual site-level cooling cost. We first built an Icepak chip-level model comparing a no-IVR GPU (control) to a GPU with four on-interposer IVRs sharing the final conversion stage at 88% efficiency. For each of four GPU TDP cases, we extracted the cold-plate heat transfer coefficient required to hold Tj at 85 °C with 25 °C coolant, then quantified the additional cooling needed when the IVRs are added. We also swept IVR efficiency at fixed TDP and cooling to isolate the impact of conversion loss on Tj. We then constructed a MATLAB system-level model of two architectures: Architecture A (48 V – 12 V – 1 V), where both conversion stages reject heat to air, and Architecture B (48 V – 4 V – 1 V), where the final 4 V – 1 V stage is on-interposer and rejects heat to the liquid loop with the GPU. Losses were aggregated from board to server (8 GPUs/server, 4 servers/rack) to a 100-rack site. Annual cooling energy and cost are computed using hourly ambient temperature data, an ambient-dependent chiller COP model with two-tier free cooling (dry cooler for liquid, waterside economizer for air), and local commercial electricity rates. Two results followed. First, the IVR architecture imposed a 3–5 °C thermal coupling penalty on the GPU, and this penalty shrinks as GPU TDP grows, because the higher cold-plate HTC required at elevated power density also more effectively removes IVR losses. Second, despite shifting more heat into the liquid loop, Architecture B yielded a lower annual cooling cost than Architecture A, and this advantage widened with increasing GPU TDP, as a greater share of system heat moves from air to the more efficient liquid path. 

Presenter

Affiliation

Title and Abstract

Nick Baker

Univ of Alabama

Keynote: Liquid-Metal Interconnects for Power Semiconductors

Abstract: Power semiconductors are traditionally manufactured using solid-metal interconnect technologies such as wire-bonding, soldering and sintering. These interconnects are vulnerable to thermo-mechanical stress and are the primary cause of failure in semiconductors. This speech presents the use of room-temperature melting, Gallium-based, liquid-metal pastes for chip-level packaging of SiC MOSFETs. All chip critical interconnects (i.e., die-attach, topside, and gate connections) are implemented using liquid metal, which remain in the liquid phase during semiconductor operation. In comparison to solder and wire-bonded devices, liquid-metal packaged SiC MOSFETs exhibit lower on-resistance, improved thermal performance, and an order-of-magnitude increase in power cycling lifetime. Liquid-metal interconnects furthermore enable new module designs due to the low temperature, non-toxic manufacturing process, and open the possibility recycling and reassembly of semiconductor chips and components. 

Pat McCluskey

Univ of Maryland

TBD

Sooan Pack

Univ of Rhode Island

Real-Time In-Situ Dual-Pulse Testing of Switching Characteristics in Phase-Shift Full-Bridge Converters via Backward Operation

Abstract: TBD

Alec Bunn

ASU

Parameterized PINNs for Warpage Prediction in Heterogeneous Multi-Chip Module Packages

Abstract: Advanced power electronics systems increasingly adopt heterogeneous multi-chip module packaging to integrate power devices, driver circuitry, control integrated circuits, and passive components. However, the resulting geometric heterogeneity introduces thermomechanical challenges due to coefficient of thermal expansion mismatch among package materials. Accurate prediction of floorplan-dependent warpage is therefore important for mechanically robust package design. Finite element analysis (FEA) remains the dominant approach for warpage analysis because of its ability to resolve detailed thermomechanical deformation fields. However, its computational cost becomes prohibitive for large-scale exploration of die size and placement configurations. Recent machine learning-based surrogate models have accelerated prediction, but existing approaches commonly rely on simplified layouts with uniformly sized dies or regular arrangements, limiting applicability to realistic heterogeneous floorplans. This work proposes a parameterized physics-informed neural network (P²INN) framework for predicting full-field package warpage directly from heterogeneous die floorplans. The proposed framework incorporates governing thermomechanical principles through minimization of total potential energy, eliminating the need for supervised deformation labels generated from FEA. The package structure consists of a substrate layer and multiple rectangular dies with varying sizes and asymmetric placements. The network takes die bounding-box coordinates and spatial query locations as input and predicts the corresponding out-of-plane warpage field. The proposed P2INN demonstrates strong agreement with FEA across 1024 randomly generated multi-die floorplans, achieving an average warpage error of 8.4%. Inference for a batch of 128 layouts sampled on (64×64) grids requires only 0.5 ms on a single NVIDIA A100 GPU, corresponding to an approximate (3.9×10⁴) speedup relative to the reference solver. These results demonstrate rapid and accurate warpage prediction across highly heterogeneous floorplans without reliance on simulation-generated training data. 

Presenter

Affiliation

Title and Abstract

Jerry Zhai

Max Epic

Keynote: Silicon Capacitor Array chiplet for Power Design Network with a Wide Voltage Range

Abstract: TBD

Yicheng Zhu

UT-Austin

Design-Oriented Modeling and Multi-Objective Optimization of Two-Phase Coupled Inductors in Multiphase PWM Converters

Abstract: Two-phase coupled inductors can achieve the same steady-state inductance as two discrete inductors with reduced core volume and improved dynamic response, which makes them advantageous in interleaved multiphase PWM converters. However, there is currently no comprehensive and systematic optimization method for two-phase coupled inductors to determine the optimal core dimensions for given design targets. To fill this gap, this talk presents a design-oriented magnetic circuit model for two-phase coupled inductors based on common-mode and differential-mode decomposition, which offers more physical insights for core geometry design compared to conventional flux analysis. The design of a two-phase coupled inductor is then formulated as a multi-objective optimization problem, aiming to minimize overall volume, power loss, and transient inductance while meeting requirements on steady-state inductance, form factor, and saturation current. The proposed design-oriented model and multi-objective optimization method are validated through comparisons with Monte Carlo simulations using ANSYS and experimental hardware results. 

Youssef Elasser

NVIDIA

Overcoming the Magnetics Bottleneck in Vertical Power Delivery for AI

Abstract: As GPU power consumption scales beyond 1 kW with core voltages continuing to decrease, vertical power delivery (VPD) has emerged as a critical architecture for minimizing I²R losses and parasitic impedance between the voltage regulator and the die. However, realizing ultra-thin VPD modules remains limited by magnetic component scaling. Unlike capacitors and semiconductors, inductors do not shrink favorably with size, making them the dominant bottleneck in achieving current densities above 2 A/mm² within sub-3 mm height envelopes. This work addresses the bottleneck through multiphase coupled inductor techniques. The Patterned-Magnetic-Flux (PMF) inductor geometry is introduced, which fully wraps the core around the winding, enabling vertical current flow while decoupling DC resistance from the air-gap design. A two-phase buck VPD prototype using the PMF inductor achieves a total module height of 3 mm with a 100 mm² footprint, operating at 1.5 MHz with 6 V to 0.8 V conversion. The prototype demonstrates 89.3% peak efficiency, 77.5% full-load efficiency at 80 A, and a power density of 0.8 A/mm². The landscape of coupled magnetic structures, including lateral flux, vertical flux, air-core, and TLVR approaches, is reviewed in the context of VPD constraints. Remaining challenges in thermal management, transient response, and further density scaling are also discussed. 

Kamyar Ahmadi

Eneira

Breaking the “Current” Barrier: Electroplated Integrated Magnetics for 3D-Hi Vertical Power Delivery

Abstract: The escalating power demands of modern computing and AI systems drive the need for advanced power delivery architectures in 3D heterogeneous integration (3D-HI). Vertical power delivery using integrated voltage regulators (IVRs) promises higher efficiency and power density, but is fundamentally limited by the current-handling capability of on-package or on-chip inductors. This work introduces electroplated integrated magnetics that break the “current” barrier for high-performance 3D-HI applications. We demonstrate ultra-thick high-aspect-ratio electroplated copper windings that achieve high winding packing factors which simultaneously enable low DC resistance (DCR) and high inductance. The fabrication process is substrate-agnostic, can successfully be realized on silicon, GaN, and PCB platforms. Being post-process CMOS compatible, it allows seamless integration with back-end-of-line (BEOL) flows. High-frequency and high-current capability is achieved through novel electroplated compositionally modulated magnetic alloys (CMA), in which resistivity and permeability are sequentially varied along the z-axis to form a virtual lamination that suppresses eddy-current losses. The resulting inductors can deliver >40 A/mm³ current density and a figure-of-merit (FOM) of 4000 nH/Ω, more than double the performance of state-of-the-art integrated magnetics, while maintaining an ultra-low profile (<200 µm). Importantly, the high current per inductor is a direct result of the thick copper conductors, which inherently carry more current per phase than thin-film alternatives. This reduces the number of phases required in multiphase IVR designs, lowering system complexity, footprint, and cost without resorting to the extreme switching frequencies that competing integrated approaches require to achieve comparable current densities. Unlike discrete inductors, which offer high current capability but prevent integration into chiplet stacks, this architecture is fully compatible with 3D-HI vertical power delivery, paving the way for compact, high-efficiency power conversion exceeding 1 kW/in³.

Presenter

Affiliation

Title and Abstract

Ahmed Abou-Alfotouh

AMD

Keynote: Power Delivery as the definitive frontier of AI Performance

Abstract: As AI infrastructure scales toward unprecedented physical and financial dimensions — with data center investment surpassing $300 billion annually and racks racing toward half a megawatt — power delivery has transitioned from a secondary support function to the definitive constraint on system performance. Advanced semiconductor node progression continues to intensify power density and thermal challenges, while lateral power delivery architectures have reached absolute physical scaling limits. This presentation argues that ultra-dense Power Delivery represents an architectural imperative. Achieving this transition demands strict hardware targets across three pillars — power density (including passive components), efficiency at scale, and reliability — underpinned by open standards and modular architecture. The work concludes with a call to the Power research community to align around ultra-dense power architectures, framing effective power delivery as the definitive frontier of AI computing. 

Imran Khan

Saras Micro Devices

Passives Technology for Vertical Power Delivery Architectures for AI and HPC PDN Solutions

Abstract: Widespread adoption of AI is driving substantial investment in hyper scale datacenters with powerful compute clusters to support growing workload demands. At the same time the size of the processor and the power density is increasing. In aggregate the energy usage has reached unprecedented levels and rising rapidly. The impact of datacenters on energy consumption is substantial with an estimated use of 176 TWh in 2023 that is expected to grow between to 325-580TWh by 2028. Raising concerns on grid capacity to meet the rising power demands. It is clear there is significant and urgent importance being given to efficiency in power delivery to processors and advancing the compute per watt performance. Maintaining optimal power integrity at higher currents and power densities across a wide range of frequencies at lower voltages poses challenges that available solutions are inadequate to address. The efficiency must be attained at higher power densities and high bandwidths while competing with board space where more of the available area is consumed by logic and memory dies. This surge has exposed the limitations of traditional power regulation and delivery architectures and the need for advanced power delivery solutions. This paper presents Saras STILE advanced technology platform to address these critical challenges. The core of STILE consists of high density capacitors and high frequency low loss inductors. The passives components are purpose designed to be directly integrated into the chip package substrate or system PCB. This paves the way for realizing advanced power and voltage regulation schemes that unlock the benefits of close to point of load with Integrated Power Delivery and Vertical Power Delivery (VPD) architectures. 

Noah Sturcken

Ferric

Powering the AI Era: High-Density Integrated Voltage Regulators

Abstract: As the demand for high-performance computing, artificial intelligence, and mobile efficiency scales, traditional off-chip power management solutions are increasingly hitting the “power wall.” This presentation explores the critical shift toward Integrated Voltage Regulators (IVRs), specifically focusing on the evolution of switched-inductor topologies that bring power conversion directly onto the processor die or within the same package. By minimizing the physical distance between the regulator and the load, IVRs effectively mitigate parasitic losses, reduce board real estate, and enable ultra-fast dynamic voltage scaling. We begin by examining the primary motivations driving this integration. Standard VRMs are limited by the parasitics of the Power Delivery Network (PDN), leading to significant I2R losses and transient voltage droops. Inductor-based IVRs address these challenges by providing high-bandwidth regulation and granular power management, allowing for per-core voltage control that significantly boosts energy efficiency in many-core architectures. The talk then transitions into recent trends and developments in integrated magnetic components, highlighted by recent industry breakthroughs. We will discuss the engineering of high-frequency, CMOS-compatible inductors, including the use of thin-film magnetic materials to enhance power density. We will also discuss recent IVR product developments, including Ferric’s state-of-the-art solutions. We will examine how these integrated voltage regulators enable in-package vertical power delivery, significantly reducing the distance current travels to the load. Finally, we look toward future opportunities for kilowatt-class power delivery. As AI processors exceed 5kW operating regimes with supply voltages well under 1V, there is an urgent need for revolutionary power delivery technology. We will explore how co-packaging IVRs within 2.5D and 3D heterogeneous systems allows for modular power scaling beyond 10 kW. Attendees will gain a comprehensive understanding of how integrated switched-inductor regulators are transforming from a niche architectural choice into a cornerstone of next-generation semiconductor design.

Presenter

Affiliation

Title

Asif Muhammad Juberi

ASU

Inorganic Electret Coating for Partial Discharge Mitigation in HIPM Substrates 

Keigo Higashida

TDK Corporation

Embeddable Low Profile Magnetics Component for IVR Applications

Toshio Hiraoka

TAIYO YUDEN CO., LTD.

Metal-Based Multilayered Coupled Inductors for IVR Applications 

Joseph Winkler

Leibniz University Hannover

A 48V-to-1V High-Power-Density DC–DC Converter Using Vertically Integrated Peek Power Brick Modules for High-Performance Computing 

Zhicheng Guo

ASU

Development of High-Voltage Wide-Bandgap Power Modules with Series-Connected Chips 

Allen Nguyen

Dartmouth

Improving Current Density in Vertical-Power-Delivery (VPD) Multiphase Coupled Inductors

Li Zhang

Virginia Tech

Advanced Medium-Voltage SiC Packaging with EMI Shielding and Electric Field Management

Atiah Yeasmin

ASU

Fan-Out Wafer-Level Packaging of 1.2 kV SiC Power MOSFET Using Functional Composite Passivation

Nafis Washir

ASU

Electric-Field Mitigation in 1.2 kV Vertical SiC MOSFET Wafer-Level Packaging Using Electret-Based Field Control

Dave Saums

DS&A LLC

Current Developments in Thermal Material Test and Characterization