Plenary P1:
Title: “Rethinking Power Delivery for Next Generation Ai Accelerators”
Presenter: Kaladhar Radhakrishnan, Intel
Abstract: Power delivery has become a first order limiter for performance scaling in modern data center chips. The rapid rise of AI and HPC workloads place far greater demands on the power delivery network than traditional solutions were designed to handle. As the AI accelerator power levels approach multiple kW, traditional motherboard voltage regulator solutions become highly inefficient. In this talk we will take a closer look at the key power delivery challenges in this segment and look at some of the novel solutions that are being developed to address these challenges.
Biography:
Kaladhar Radhakrishnan joined Intel in 2000 soon after receiving his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign. He is currently a Fellow with the Technology Development group and his primary research interests include microprocessor power delivery, and computational electromagnetics which was the focus of this dissertation work. More recently, his areas of focus have been in integrated voltage regulation and magnetic inductors.
Plenary P2:
Title: “Scaling Vertical Power Delivery for Ai Computing: a PPACt‑Driven Materials and Process Perspective”
Presenter: Yi Zheng, Applied Materials
Abstract: AI and HPC workloads are driving unprecedented demands on power density, efficiency, and dynamic response, making power delivery a defining constraint at the system level. This presentation examines how wafer processing, 3D integration and advanced packaging are reshaping integrated power electronics to meet these challenges, linking materials innovation and fabrication process flows with chip package system co optimization for high volume manufacturing. The presentation spans monolithic Integrated Voltage Regulators (IVRs) and heterogeneous integration of active and passive components, including monolithic buck converters, low voltage MOSFETs, GaN devices, and the co integration of inductors and deep trench capacitors at wafer or panel level. Emphasis is placed on vertical integration strategies that reduce power delivery path parasitics, improve transient performance, and enable scalable solutions for AI accelerators and high performance computing platforms Technology inflections are discussed through the lens of PPACt—Power, Performance, Area, Cost, and Time to market—highlighting both the opportunities and constraints introduced by advanced packaging. The keynote concludes with a call to action on high value problems in materials compatibility, process integration, thermal electrical co optimization, yield enhancement, and metrology, where focused industry–academic collaboration is essential to sustain AI/HPC scaling.
Biography:
Plenary P3:
Title: “Heterogeneous Integration of Vertical Power Delivery for AI and High Performance Computing”
Presenter: Cian Ó Mathúna, Tyndall National Institute
Abstract: Vertical power delivery has emerged as an essential element of integrated power management for high performance computing and AI. This is being enabled by advances in the dramatic miniaturisation and heterogeneous integration of dc-dc power converters in processor substrates, packages and interposers. This move to integration of power delivery is further facilitating the concept of granular power whereby large arrays of miniaturised dc-dc converters are integrated within the processor package, or the underlying motherboard, thereby enabling significant reduction in overall system energy. A key enabler has been developments in the miniaturisation and integration of power magnetics so that they effectively disappear. Initially the talk will present the current range of integrated power formats – from power modules under the motherboard or package substrate to PCB-embedded power and onto integrated power in interposers. An important enabler is the emergence of integrated magnetics technologies (including magnetics-on-silicon (MagIC), PCB-embedded magnetics, in-package magnetics and ultra-thin chip inductors). Approaches to heterogeneous integration of PMIC, magnetics and capacitors to be discussed will include flip chip assembly, substrate embedding, micro-transfer printing and monolithic fabrication on PMICs and/or in interposers. Performance trade-offs for the different solutions will be presented. Finally, key challenges to be addressed, both from a technology and supply-chain perspective, will be discussed.
Biography:
Prof. Cian Ó Mathúna is Director of Integrated Power and Energy Systems Research at Ireland’s Tyndall National Institute, University College Cork. His team’s research, into the miniaturisation and integration of magnetics onto silicon, and in PCBs, has contributed to disruptive global developments of integrated power management for processors in portable and high performance computing. Using semiconductor fabrication of thin-film magnetics, the team have made bulky magnetic components disappear onto silicon chips. Referred to as “MagIC”, Tyndall’s magnetics-on-silicon technology has been licensed to global electronics companies and foundries. In 2008, Ó Mathúna founded the International Workshop on Power Supply on Chip (PwrSoC), now a flagship event for IEEE PELS and PSMA. Through his leadership, and collaborations with world-leading industry players in Europe, USA and Asia, Ó Mathúna has influenced the emergence of global supply-chains for PwrSoC directly resulting in high-volume production of magnetics-on-silicon in commercial product. In 2013, he was elevated to IEEE Fellow with the citation “for leadership in the development of power supply using micromagnetics on silicon”. In 2021, he received the IEEE PELS Technical Achievement Award for “Integration and Miniaturisation of Switching Power Converters” as well as an EARTO (European Association of Research and Technology Organisations) Impact Innovation Award.
Plenary P4:
Title: “Integrated Vertical Power Delivery for AI Datacenters – Challenges & Opportunities”
Presenter: Madhavan Swaminathan, Pennsylvania State University
Abstract: As we enter the artificial intelligence era, power is becoming a significant crisis with AI data centers expected to draw more than 20% of the power from the grid produced in the United States and much more worldwide. What is therefore required are power efficient system architectures where power efficiencies are maximized. Heterogeneous Integration combined with power electronics plays a very critical role here. In this presentation, various methods for power delivery focused on AI datacenters will be discussed with a focus on integrated vertical power delivery in the package to maximize efficiencies.
Biography:
Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center www.chimes.psu.edu.
Prior to joining Penn State, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC) – a graduated NSF-Engineering Research Center (ERC), Georgia Tech (GT). Prior to GT, he was with IBM working on packaging for supercomputers.
Prof. Swaminathan’s interdisciplinary research on semiconductor packaging and systems integration over the years have resulted in 650+ technical publications, 200+ invited presentations (seminars, keynotes, panels), 3 books, 5 book chapters, 31 patents, 35 best paper and student paper awards, 5 GT awards, 2 start-ups, and several international recognitions with the recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (highest technical field award in packaging) for “contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems”. He is also the founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He serves as an advisor to India Semiconductor Mission, member of External Advisory Board for Move2THz (an EU initiative), and is on the advisory board of 3DGS and Claros.
He received his MS and PhD degrees in Electrical Engineering from Syracuse University, USA.
Plenary P5:
Title: “3D Panel Level Packaging and Advanced Compact 3D Module Architectures for Next Generation Power Electronics”
Presenter: Stephen Coates, Yuxuan Semi
Abstract: The rapid growth of electrification, AI infrastructure and renewable energy systems is driving demand for smaller, more reliable and easier to manufacture high power packaging technologies. Conventional power module approaches are starting to hit limitations around electrical parasitics, thermal performance, mechanical stress and manufacturing scalability. This paper looks at emerging innovations in 3D panel level packaging and compares them with more traditional power module manufacturing methods. Particular focus is placed on reducing electrical and mechanical stress through advanced interconnect structures, embedded conductor technologies and thick copper processing for high current applications. The paper also touches on integration opportunities for lateral GaN devices and other wide bandgap technologies within advanced packaging architectures. Alongside this, the paper reviews new approaches for very high power and high voltage 3D module integration, where reducing footprint, weight and overall system size is becoming increasingly important. These include vertical architectures with embedded inductors, multilayer ceramic substrates with fine metallisation for GaN flip chip interconnection and wider SiP integration, and ceramic clip structures that offer more direct cooling than copper clips that rely on a dielectric TIM. Together, these approaches support much smaller, higher power density modules whilst still maintaining long-term reliability. The work also discusses practical manufacturing considerations, rapid prototyping capability, smaller batch production flexibility and future directions for scalable, high reliability 3D power electronics integration.
Biography:
With 37 years of global experience across Asia, North America, and Europe, and now living in Hsinchu Taiwan, Stephen Coates has held senior executive positions in some of the world’s most respected semiconductor firms.
Most recently, his leadership was instrumental in the $823 million acquisition of GaN Systems by Infineon, where he served as VP Global Ops & GM Asia in GaN Systems, followed by VP Foundry Sourcing at Infineon Taiwan. Stephen now runs his own company, YuXuan Semi, based in Taipei & Hsinchu Science Park.
Stephen has built and managed complex global supply chains, launched fabless and backend ecosystems in Asia, and scaled operations from concept to high-volume production, particularly for GaN, SiC, Si-based power devices, mature nodes in Si and Si/Compound photonics and all aspects of assembly & test (OSAT). Stephen has a track record demonstrating business & operational excellence and execution through the commercialization of emerging technologies.
He is a regular speaker at SEMICON Taiwan, has been an invited speaker at the TSMC Technology Symposium, he guest lecturers at NYMCT University in Hsinchu, is a founding member of SEMI Taiwan’s Compound Opto & Power Committee and holds multiple device and packaging patents.
Stephen obtained a Bachelor of Engineering in Electrical & Electronic Engineering and then also completed a postgraduate program in Manufacturing Excellence at Nottingham Trent University in England.
Plenary P6:
Title: “AI Trajectory and its Demands on Power Delivery”
Presenter: Rinkle Jain, NVIDIA
Abstract: As AI growth continues, the petaFLOPs and power demand trajectory are presented. The impending bottlenecks as well as key constructs circumventing them to sustain such unprecedented scaling/ density are delineated. Further, we observe salient workload characteristics and the unique thrust for beyond-reticle-size systems despite their high degree of parallelism. What are each of its implications to power delivery scheme? In these intense races of various technologies and cross functionalities, let’s find out how power delivery can enable this at the forefront.
Biography:
Rinkle Jain (Member, IEEE) received the M.S. and Ph.D. degrees in electrical engineering with an emphasis on power electronics from the University of Minnesota, Minneapolis, MN, USA, in 2003 and 2006, respectively.,She joined the Intel Labs, Hillsboro, OR, USA, as a Research Scientist, upon graduation. She is currently a Principal Engineer with the Advanced Computing and Graphics Group, Intel. Her work focuses on integrated power converters on CMOS and deep n-well processes. Her expertise includes switched capacitor voltage regulators, control theory and modeling applied to switched systems, functional integration of multiple magnetic components and their fabrication, including composite materials for high power applications, and thin film inductors. She holds several patents and invited publications in refereed journals on the above topics.,Dr. Jain serves as a member of the Technical Program Committee (TPC) for premier conferences, such as IEEE Custom Integrated Circuits Conference (CICC) and IEEE Energy Conversion Congress and Exposition (ECCE). She serves as the Chair of the Board of Trustees of the Cedarwood Waldorf School. She has long been associated with the IEEE’s Power Supply on Chip Workshop.
