S1: Plenary I : Design for Power
Title: “Power Module Finite-Element Predictive Modeling”
As the world transitions toward system electrification to further reduce energy waste, the SiC power module market demand has continued to exponentially grow across the automotive, industrial, aerospace, and energy markets. As such, the need for robust, predictive modeling tools is a key enabler in the success of power module products and technology. These modeling tools can help predict performance characteristics for customers, optimize design materials/geometries/features to take advantage of the superior characteristics of SiC, estimate fatigue and lifetime, reduce time to market by minimizing testing time and resources, and reduce product cost by minimizing unnecessary over design.
The fundamental challenge of simulating SiC power module characteristics is that they encompass several different fields including electrical, mechanical, thermal, chemical, and material science as well as coupling between each area. Thus, the simulation tools must be capable of coupling multi-physics models, boundary conditions, and material properties to accurately predict power module characteristics.
In this presentation, examples of multi-physics predictive modeling will be presented highlighting tradeoffs, optimization, and performance of SiC power modules.
Dr. Brandon Passmore, Wolfspeed
Brandon Passmore completed his B.S. in Electrical Engineering from Arkansas State University in 2003, M.S. in Microelectronics and Photonics in 2005, and Ph.D. in Microelectronics and Photonics in 2008. His M.S. and Ph.D. work focused on developing novel optical defect recognition techniques for laser diodes and mid-infrared InGaAs/GaAs quantum dot photodetectors, respectively. He then completed a postdoc at Sandia National Laboratories where he worked on developing novel photonic devices and metamaterials for mid-infrared imaging applications. Brandon has been with Wolfspeed since 2010 where he is a Sr. Hardware Development Engineering Manager leading the Design Engineering Team in the Power Modules business unit. At Wolfspeed, his group focuses on developing new SiC power modules rated from 650 V to 1.7 kV and 50 A to 800 A and beyond. In addition, his group has been heavily involved in several projects focused on developing new packaging designs, modeling techniques, materials, and processes to fully optimize the performance of SiC power devices. Some of these technologies include electrical-thermal-mechanical multi-physics modeling, wire bondless technologies, new die attach and substrate technologies, and high heat transfer and advanced cooling technologies for the advancement of high performance SiC power modules. He has accumulated over fifty refereed conference and journal publications and fourteen patents over his career.
Title: “Integrated Power Delivery for AI Computing: Technology Gaps & Opportunities”
The power delivery requirements for the early microprocessors and FPGAs were rudimentary due to the relatively low power levels. However, several decades of exponential scaling powered by Moore’s law have greatly increased the power requirements and the complexity of the power delivery scheme. The breakdown in Dennard scaling in the mid-2000s has ushered in the multicore era which has increased the number of cores and the power consumption. The steady growth in the power levels and the number of power rails have increased the power delivery challenges. With AI compute engines emerging, the power delivery requirements are becoming even more challenging. Integrated voltage regulators (IVRs) have emerged as a key power delivery technology to address some of these challenges which include IVR schemes implemented on-die ranging from the simple power gate to fully integrated switching regulators. With advanced heterogeneous packaging technologies emerging, the current demand in the package is continuously increasing posing challenges for managing IR drops, voltage droop, thermal design power and others.
This presentation will cover advanced packaging technologies that are being developed and needed to enable heterogeneous integration and their impact on power delivery. Machine learning methods emerging for designing IVRs and power delivery networks will be addressed as well.
Prof. Madhavan Swaminathan, Georgia Tech
Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (https://caeml.illinois.edu/) and Theme Leader for Heterogeneous Integration, at the SRC/DARPA JUMP ASCENT Center (https://ascent.nd.edu/). Prior to joining GT, he was with IBM working on packaging for supercomputers.
He is the author of 550+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies (Jacket Micro Devices and E-System Design), and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS) currently in its 20th year.
Prof. Swaminathan is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society.
His research has been recognized with 28 best paper awards. In addition, his most recent awards include the GT ECE Distinguished Faculty Achievement Award presented to a senior faculty member who has made significant contributions throughout his/her career (2022), D. Scott Wills ECE Distinguished Mentor Award (2018), the Georgia Tech Outstanding Achievement in Research Program Development Award (2017), the Distinguished Alumnus Award from the National Institute of Technology Tiruchirappalli (NITT) in India (2014), and the Outstanding Sustained Technical Contribution Award from the IEEE Electronics Packaging Society (2014).
He received his MS and PhD degrees in Electrical Engineering from Syracuse University.
S6: Plenary II: Improved Electrical Performance for Power
Title: “PCB Based Integrated Magnetics.”
In today’s market, most power electronics products are custom designed with significant nonrecurrent engineering and also subjected to labor-intensive manufacturing processes. The major road blocks are hinged on the ability to integrate large and bulky magnetic components in a form suitable for automation. Suffice it to say that the design practice for magnetic components has remained largely the same for the past five decades.
With recent advances in wide-band-gap (WBG) power semiconductor devices, we have witnessed significant increase in switching frequency while achieving higher efficiency and power density compared to the current practice using silicon counterparts. With significantly higher operating frequency, the integration of magnetic components with embedded windings in the PCB is feasible for wide range of applications. Design trade-offs, previously considered neither practical nor conceivable, can be realized, not only with significant gain in efficiency and power density, but also with drastic improvements of EMI/EMC and manufacturability.
The PCB based magnetics design practices and tradeoffs are quite different from the conventional practice. Certain benefits and limitations will be highlighted in this talk.
Professor Fred C. Lee, Virginia Tech
Dr. Lee is a University Distinguished Professor Emeritus at Virginia Tech. He is a member of the U.S. National Academy of Engineering, U.S. National Academy of Inventors, an academician of Taiwan’s Academia Sinica, and a foreign member of the Chinese Academy of Engineering, China. Dr. Lee founded the Center for power electronics and led a program that encompasses research, technology development, educational outreach, industry collaboration, and technology transfer. To date, more than 230 companies worldwide have benefited from this industry partnership program.
Dr. Lee has supervised to completion 89 Ph.D. and 93 M.S. students. He holds over 100 US patents, and has published over 330 journal articles and more than 760 refereed technical papers. His research interests include high-frequency power conversion, magnetics and EMI, distributed power systems, renewable energy, power quality, high-density electronics packaging and integration, and modeling and control.
Dr. Lee is a recipient of the 2015 IEEE Medal in Power Engineering “for contributions to power electronics, especially high-frequency power conversion.”
Title: “Future of Packaging and the Role of Power Integration”
Moore’s law has been the driving engine for science, technology, manufacturing, hardware, software, systems, and applications, contributing to the prosperity of thousands of individuals and 100s corporations in dozens of countries. As Moore’s Law benefits begin to slow down, not for the doubling of transistors, but for decreasing transistor speeds and the resulting slower computing performances, packaging is playing a very critical and strategic role, unlike in the past. Prof. Tummala refers to it as Moore’s Law for packaging. Just like Moore’s Law has both doubling of transistors and simultaneous cost reduction, from node to node every 18-24 months, Moore’s Law for systems packaging or interconnections has been doubling I/Os every 5 years. Interconnections have been driven by computing systems and within computing systems, between logic and memory for the highest bandwidth at lowest power. The new era of artificial intelligence, mimicking the human brain with several orders better computer performance, is yet another reason for the next Moore’s Law. Currently, the best Moore’s Law for packaging is with wafer-based silicon packaging. But silicon-based packaging has many limitations at the material, device, circuit, and system levels. Glass panel packaging has been developed by Georgia Tech and its partners and is going into production in 2023. Power efficiency of computing systems is getting to be as important as performance, requiring dramatically-improved power components and their integration into the packages. This talk will highlight the next Moore’s Law for packaging that is necessary to achieve exponential growth in computing performance.
Professor Rao Tummala, Georgia Tech
Prof. Rao Tummala is an Emeritus Professor and former Director of Packaging Research Center, Georgia Tech, which he served for 28 years. Before that, he was at IBM for 25 years, where he was the IBM Fellow and Director of Advanced Packaging Lab. He has published about 800 technical papers and invented technologies that resulted in over 110 patents. He also wrote the first modern textbook in Microelectronics packaging, Microelectronics Packaging Handbook (McGraw-Hill 1988); two undergrad textbooks on Fundamentals of Microsystem Packaging (2001, 2019); and the 1st book introducing the concept of SOP, Introduction to System-on-Package (2006). He graduated 900 Ph. D & MS packaging engineers to supply to almost every electronic company in US. He received more than 50 Industry, Academic and Professional Society awards. He is a member of National Academy of Engineering and IEEE Fellow. He was also President of IEEE CPMT and IMAPS Societies. IEEE named him Father of Modern Packaging and created IEEE Rao Tummala Electronic Packaging Award, a technical field award.
S14: Plenary III: Improved Electrical Performance for Power
Title: “Superior Heat Dissipation by Low-Pressure Ag Sinter Joining and Real-Time AI Lifetime Prediction for Sic Power Module”
Various interconnection technologies and basic sciences for advanced semiconductors and power devices have been explored in Suganuma laboratory for many years. In the present talk, latest three subjects for power electronics will be briefly introduced as Ag sinter joining for power assembly, and thermal property measurement/management and performance of Ag based TIM, and AE monitoring of power devices and real-time life prediction with AI technology.
Sinter joining has expanded into a new stage while it was developed for ceramic/metal joining in 1982 . F3D laboratory has focused on low temperature/low or no pressure joining with Ag micron size particles . One of the applications from our Ag sinter joining is the super-heat dissipation interconnection without any interface metallization. A direct bonding of Si and Al with the Ag paste becomes possible at 200 ºC without any pressure. Ag sintered inter-layer can cool devices with its excellent thermal conductivity beyond 150 W/mK.
Acoustic emission (AE) based condition monitoring is a popular method to inspect a material health condition in many areas. AE signals convey abundant information such as rise time, AE energy, and AE peak frequency, related to the degradation process. In this work, the authors group first combined the AE monitoring and a deep learning model – Gated Recurrent Unit (GRU) to monitor in order to predict the failure of power module as shown in Figure 1 . Specifically, the time-series data consisting of junction temperature, electric power, thermal resistance, and AE parameters were obtained during power cycling test. The proposed method (a) automatically extracts common or different time-series patterns among devices and estimates device states, and (b) effectively predicts failures by switching prediction models according to changes in device states.
For advanced power devices, thermal performance has a key for their sound operation. Thermal performance measurement method has been developed especially for power applications, which has been under the national project for ISO standardization. In addition to thermal managements/performance measurements, AE sensing in device operation will provide life time prediction, which is expected for high power application such data center devices and power supply .
1. K. Suganuma et al, J. Amer. Ceram. Soc., 66 (1983), c117.
2. K. Suganuma et al, Microelectron. Reliab., 52(2012), 375.
3. C. Choe et al, IEEE Transactions on Power Electronics, 36(2021), 4420.
Professor Katsuaki Suganuma, University of Osaka, Japan
Professor Katsuaki Suganuma received the degree of Dr. Engineer from Tohoku University in 1982. He became a research assistant of ISIR (Institute of Scientific and Industrial Research), Osaka University in 1982, an associate professor of National Defense Academy in 1986, and a professor of ISIR of Osaka University in 1996. He was the director of Nanotechnology Center in 2007-2009 and was the deputy director of ISIR in 2010-2012. He has worked on lead-free soldering, conductive adhesive, power electronics packaging and printed electronics and published several books both on lead-free soldering and on printed electronics. He is currently in charge of the several projects such as Conductive adhesive testing methods standardization (JEITA), Printed electronics standardization IEC TC119 Japan committee (JEITA), Chairman of Printed Electronics on Circuits (JPCA) and WGB system integration consortium.
Title: “Emerging Power Electronics Packaging and System Integration for Automotive Applications”
Semiconductor power devices and modules are critical components of power electronics in electrified automotive vehicles. The building blocks of automotive power electronics, key drivers for power packaging, design/ materials/ process considerations for power modules will be discussed in this talk. Emerging automotive power trends and key technical challenges associated with power modules design and fabrication will be presented. System integration concepts and few of the promising trends for automotive application will also be discussed as a part of this presentation.
Dr. Mahadevan (Devan) Iyer, Amkor
Devan Iyer joined Amkor in 2021 as a Vice President of R&D for Wirebond and Power business with his 30+ years of experience in global semiconductor engineering and management. Prior to joining AMKOR, Devan as Corporate Vice president of Texas Instruments, led TI’s Semiconductor Packaging organization and was responsible for R&D, product qualification and ramp to manufacturing covering wire bond, flip chip leadframe and substrate based packages, wafer bumping and wafer scale packages for all of TI’s businesses and customers. Devan has a Ph.D degree for his thesis on novel interconnects for GHz multi chip modules and an MBA degree. Devan has more than 150 technical publications, 30 patents and has given several keynote and invited talks in leading conferences and industry meetings.